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cat1024, cat1025 ? 2009 scillc. all rights reserved. 1 doc. no. md-3008 rev. q characteristics subject to change without notice supervisory circuits with i 2 c serial 2k-bit cmos eeprom and manual reset features precision power supply voltage monitor ? 5v, 3.3v and 3v systems ? five threshold voltage options active high or low reset ? valid reset guaranteed at v cc = 1v 400khz i 2 c bus 2.7v to 5.5v operation low power cmos technology 16-byte page write buffer built-in inadvertent write protection ? wp pin (cat1025) 1,000,000 program/erase cycles manual reset input 100 year data retention industrial and extended temperature ranges green packages available with nipdau lead finished for ordering information details, see page 19. description the cat1024 and cat1025 are complete memory and supervisory solutions for microcontroller-based systems. a 2k-bit serial eeprom memory and a system power supervisor with brown-out protection are integrated together in low power cmos techno? logy. memory interface is via a 400khz i 2 c bus. the cat1025 provides a precision v cc sense circuit and two open drain outputs: one (reset) drives high and the other (reset ) drives low whenever v cc falls below the reset threshold voltage. the cat1025 also has a write protect input (wp). write operations are disabled if wp is connected to a logic high. the cat1024 also provides a precision v cc sense circuit, but has only a reset output and does not have a write protect input. the power supply monitor and reset circuit protect memory and system controllers during power up/down and against brownout conditions. five reset threshold voltages support 5v, 3.3v and 3v systems. if power supply voltages are out of tolerance reset signals become active, preventing t he system microcontroller, asic or peripherals from operating. reset signals become inactive typically 200ms after the supply voltage exceeds the reset threshold level. with both active high and low reset signals, interface to microcontrollers and other ics is simple. in addition, the reset pin or a separate input, mr , can be used as an input for push-button manual reset capability. the cat1024/25 memory features a 16-byte page. in addition, hardware data protection is provided by a v cc sense circuit that prevents writes to memory whenever v cc falls below the reset threshold or until v cc reaches the reset threshold during power up. available packages include an 8-pin pdip and a surface mount 8-pin so, 8-pin tssop, 8-pin tdfn and 8-pin msop packages. the tdfn package thick- ness is 0.8mm maximum. tdfn footprint is 3x3mm.
cat1024, cat1025 doc. no. md-3008 rev. q 2 ? 2009 scillc. all rights reserved. characteristics subject to change without notice block diagram threshold voltage option part dash number minimum threshold maximum threshold -45 4.50 4.75 -42 4.25 4.50 -30 3.00 3.15 -28 2.85 3.00 -25 2.55 2.70 pin configuration dip package (l ) soic package (w ) tssop package (y ) msop package (z ) mr 1 8 v cc reset 2 7 nc nc 3 6 scl v ss 4 5 sda cat1024 mr 1 8 v cc reset 2 7 wp reset 3 6 scl v ss 4 5 sda cat1025 (bottom view) tdfn package: 3mm x 3mm 0.8mm maximum height - (zd4) v cc 8 1 mr nc 7 2 reset scl 6 cat1024 3 nc sda 5 4 v ss v cc 8 1 mr wdi 7 2 reset scl 6 cat1025 3 reset sda 5 4 v ss 2kbit d out ack senseamps shift registers control logic word address buffers start/stop logic eeprom v cc externa l load column decoders xdec data in storage highvoltage/ timing contr ol v ss sda reset controller precision vcc monitor state counters slave address comparators sc l reset* * cat1025 only reset mr wp*
cat1024, cat1025 ? 2009 scillc. all rights reserved. 3 doc. no. md-3008 rev. q characteristics subject to change without notice pin description reset/ reset : reset outputs (reset cat1025 only) these are open drain pins and reset can be used as a manual reset trigger input. by forcing a reset condition on the pin the device will initiate and maintain a reset condition. the reset pin must be connected through a pull-down resistor, and the reset pin must be connected through a pull-up resistor. sda: serial data address the bidirectional serial data/address pin is used to transfer all data into and out of the device. the sda pin is an open drain output and can be wire-ored with other open drain or open collector outputs. scl: serial clock serial clock input. mr : manual reset input manual reset input is a debounced input that can be connected to an external source for manual reset. pulling the mr input low will generate a reset condition. reset outputs are active while mr input is low and for the reset timeout period after mr returns to high. the input has an internal pull up resistor. wp (cat1025 only): write protect input when wp input is tied to v ss or left unconnected write operations to the entire ar ray are allowed. when tied to v cc , the entire array is protected. this input has an internal pull down resistor. pin function pin name function nc no connect reset active low reset input/output v ss ground sda serial data/address scl clock input reset active high reset output (cat1025 only) v cc power supply wp write protect (cat1025 only) mr manual reset input operating temperature range industrial -40oc to 85oc extended -40oc to 125oc cat10xx family overview device manual reset input pin watchdog watchdog monitor pin write protection pin independent auxiliary voltage sense reset: active high and low eeprom cat1021 sda 2k cat1022 sda 2k cat1023 wdi 2k cat1024 2k cat1025 2k cat1026 2k cat1027 wdi 2k for supervisory circuits with embedded 16k eeprom, please refer to the cat1161, cat1162 and cat1163 data sheets.
cat1024, cat1025 doc. no. md-3008 rev. q 4 ? 2009 scillc. all rights reserved. characteristics subject to change without notice absolute maximum ratings (1) parameters ratings units temperature under bias ?55 to +125 oc storage temperature ?65 to +150 oc voltage on any pin with respect to ground (2) ?2.0 to v cc + 2.0 v v cc with respect to ground ?2.0 to 7.0 v package power dissipation capability (t a = 25c) 1.0 w lead soldering temperature (10 secs) 300 oc output short circuit current (3) 100 ma d.c. operating characteristics v cc = 2.7v to 5.5v and over the recommended temp erature conditions unless otherwise specified. symbol parameter test conditions min typ max units i li input leakage current v in = gnd to v cc -2 10 a i lo output leakage current v in = gnd to v cc -10 10 a i cc1 power supply current (write) f scl = 400khz v cc = 5.5v 3 ma i cc2 power supply current (read) f scl = 400khz v cc = 5.5v 1 ma i sb standby current vcc = 5.5v, v in = gnd or v cc 40 a v il (4) input low voltage -0.5 0.3 x v cc v v ih (4) input high voltage 0.7 x vcc v cc + 0.5 v v ol output low voltage (sda, reset ) i ol = 3ma v cc = 2.7v 0.4 v v oh output high voltage (reset) i oh = -0.4ma v cc = 2.7v v cc - 0.75 v cat102x-45 (v cc = 5.0v) 4.50 4.75 v cat102x-42 (v cc = 5.0v) 4.25 4.50 cat102x-30 (v cc = 3.3v) 3.00 3.15 cat102x-28 (v cc = 3.3v) 2.85 3.00 v th reset threshold cat102x-25 (v cc = 3.0v) 2.55 2.70 v rvalid reset output valid v cc voltage 1.00 v v rt (5) reset threshold hysteresis 15 mv notes: (1) stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. these are stress ra tings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. exposure to any absolute maximum rating for extended pe riods may affect device performance and re liability. (2) the minimum dc input voltage is ?0.5v. during transitions, inputs may undershoot to ?2.0v for periods of less than 20 ns. m aximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. (3) output shorted for no more than one second. no more than one output shorted at a time. (4) v il min and v ih max are reference values only and are not tested. (5) this parameter is tested initially and after a design or process change that affects the parameter. not 100% tested.
cat1024, cat1025 ? 2009 scillc. all rights reserved. 5 doc. no. md-3008 rev. q characteristics subject to change without notice capacitance t a = 25oc, f = 1.0mhz, v cc = 5v symbol test test conditions max units c out (1) output capacitance v out = 0v 8 pf c in (1) input capacitance v in = 0v 6 pf ac characteristics v cc = 2.7v to 5.5v and over the recommended temper ature conditions, unless otherwise specified. memory read & write cycle (2) symbol parameter min max units f scl clock frequency 400 khz t sp input filter spike suppression (sda, scl) 100 ns t low clock low period 1.3 s t high clock high period 0.6 s t r (1) sda and scl rise time 300 ns t f (1) sda and scl fall time 300 ns t hd; sta start condition hold time 0.6 s t su; sta start condition setup time (for a repeated start) 0.6 s t hd; dat data input hold time 0 ns t su; dat data input setup time 100 ns t su; sto stop condition setup time 0.6 s t aa scl low to data out valid 900 ns t dh data out hold time 50 ns t buf (1) time the bus must be free before a new transmission can start 1.3 s t wc (3) write cycle time (byte or page) 5 ms notes: (1) this parameter is characterized init ially and after a design or process change that affects the parameter. not 100% tested. (2) test conditions according to ?ac test conditions? table. (3) the write cycle time is the time from a valid stop conditi on of a write sequence to the end of the internal program/erase c ycle. during the write cycle, the bus interface circuits ar e disabled, sda is allowed to remain hi gh and the device does not respond to its slav e address.
cat1024, cat1025 doc. no. md-3008 rev. q 6 ? 2009 scillc. all rights reserved. characteristics subject to change without notice reset circuit ac characteristics symbol parameter test conditions min typ max units t purst power-up reset timeout note 2 130 200 270 ms t rdp v th to reset output delay note 3 5 s t glitch v cc glitch reject pulse width note 4, 5 30 ns mr glitch manual reset glitch immunity note 1 100 ns t mrw mr pulse width note 1 5 s t mrd mr input to reset output delay note 1 1 s power-up timing (5), (6) symbol parameter test conditions min typ max units t pur power-up to read operation 270 ms t puw power-up to write operation 270 ms ac test conditions reliability characteristics symbol parameter reference test method min max units n end (5) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (5) data retention mil-std-883, test method 1008 100 years v zap (5) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (5)(7) latch-up jedec standard 17 100 ma notes: (1) test conditions according to ?ac test conditions? table. (2) power-up, input reference voltage v cc = v th , reset output reference voltage and load according to ?ac test conditions? table (3) power-down, input reference voltage v cc = v th , reset output reference voltage and load according to ?ac test conditions? table (4) v cc glitch reference voltage = v thmin ; based on characterization data (5) this parameter is characterized init ially and after a design or process change that affects the parameter. not 100% tested. (6) t pur and t puw are the delays required from the time v cc is stable until the specified memory operation can be initiated. (7) latch-up protection is provided for stresses up to 100ma on input and output pins from -1v to v cc + 1v. parameter test conditions input pulse voltages 0.2v cc to 0.8v cc input rise and fall times 10ns input reference voltages 0.3v cc , 0.7v cc output reference voltages 0.5v cc output load current source: i ol = 3ma; c l = 100pf
cat1024, cat1025 ? 2009 scillc. all rights reserved. 7 doc. no. md-3008 rev. q characteristics subject to change without notice device operation reset controller description the cat1024/25 precision r eset controllers ensure correct system operation during brownout and power up/down conditions. they are configured with open drain reset outputs. during power-u p, the reset outputs remain active until v cc reaches the v th threshold and will continue driving the outputs for approximately 200ms (t purst ) after reaching v th . after the t purst timeout interval, the device will cease to drive t he reset outputs. at this point the reset outputs will be pulled up or down by their respective pull up/down resistors. during power-down , the reset outputs will be active when v cc falls below v th . the reset output will be valid so long as v cc is >1.0v (v rvalid ). the device is designed to ignore the fast negative going v cc transi- ent pulses (glitches). reset output timing is shown in figure 1. manual reset operation the reset pin can operate as reset output and manual reset input. the input is edge triggered; that is, the reset input will initiate a reset timeout after detecting a high to low transition. when reset i/o is driven to the active state, the 200ms timer will begin to time the reset interval. if external reset is shorter than 200ms, reset outputs will remain active at least 200ms. the cat1024/25 also have a separate manual reset input. driving the mr input low by connecting a pushbutton (normally open) from mr pin to gnd will generate a reset condition. the input has an internal pull up resistor. reset remains asserted while mr is low and for the reset timeout period after mr input has gone high. glitches shorter than 100ns on mr input will not ge- nerate a reset pulse. no external debouncing circuits are required. manual reset operation using mr input is shown in figure 2. hardware data protection the cat1024/25 supervisors have been designed to solve many of the data corrupt ion issues that have long been associated with serial eeproms. data corruption occurs when incorrect data is stored in a memory location which is assumed to hold correct data. whenever the device is in a reset condition, the embedded eeprom is disabled for all operations, including write operations. if the reset output(s) are active, in progress communications to the eeprom are aborted and no new communications are allowed. in this condition an internal write cycle to the memory can not be started, but an in progress internal non- volatile memory write cycle can not be aborted. an internal write cycle initiated before the reset condition can be successfully finished if there is enough time (5ms) before v cc reaches the minimum value of 2v. in addition, the cat1025 includes a write protection input which when tied to v cc will disable any write operations to the device.
cat1024, cat1025 doc. no. md-3008 rev. q 8 ? 2009 scillc. all rights reserved. characteristics subject to change without notice figure 1. reset output timing figure 2: mr operation and timing glitch t v cc purst t purst t rpd t rvalid v v th rese t rese t rpd t mr reset reset t mrd t purst t mrw
cat1024, cat1025 ? 2009 scillc. all rights reserved. 9 doc. no. md-3008 rev. q characteristics subject to change without notice embedded eeprom operation the cat1024 and cat1025 feature a 2-kbit embedded serial eeprom that supports the i 2 c bus data transmission protocol. this inter-integrated circuit bus protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. the transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. both the master device and slave device can operate as either transmitter or receiver, but the master device controls which mode is activated. i 2 c bus protocol the features of the i 2 c bus protocol are defined as follows: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat1024/25 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the master begins a transmission by sending a start condition. the master sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are programmable in metal and the default is 1010. the last bit of the slave address specifies whether a read or write operation is to be performed. when this bit is set to 1, a read operation is selected, and when set to 0, a write operation is selected. after the master sends a start condition and the slave address byte, the cat1024/25 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. the cat1024/25 t hen perform a read or write operation depending on the r/w bit. figure 3. bus timing figure 4. write cycle timing t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh t wr stop condition start condition address ack 8th bit byte n s c l s d a
cat1024, cat1025 doc. no. md-3008 rev. q 10 ? 2009 scillc. all rights reserved. characteristics subject to change without notice acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat1024/25 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat1024/25 begins a read mode it transmits 8 bits of data, releases the sda line and monitors the line for an acknowledge. once it receives this acknowledge, the cat1024/25 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmis? sion and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends a 8-bit address that is to be written into the address pointers of the device. afte r receiving another acknow- ledge from the slave, the master device transmits the data to be written into the addressed memory location. the cat1024/25 acknowledges once more and the master generates the stop condition. at this time, the device begins an internal programming cycle to non- volatile memory. while the cycle is in progress, the device will not respond to any request from the master device. figure 5. start/stop timing figure 6. acknowledge timing figure 7: slave address bits start bit sd a stop bit scl acknowledge 1 sta r t scl from master 89 data output from transmitter data output from receiver 1 0100 00r/w default configuration
cat1024, cat1025 ? 2009 scillc. all rights reserved. 11 doc. no. md-3008 rev. q characteristics subject to change without notice page write the cat1024/25 writes up to 16 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial byte is transmitted, the master is allowed to send up to 15 additional bytes. after each byte has been tran smitted, the cat1024/25 will respond with an acknowledge and internally increment the lower order address bits by one. the high order bits remain unchanged. if the master transmits more than 16 bytes before sending the stop condition, the address counter ?wraps around,? and previously transmitted data will be overwritten. when all 16 bytes are received, and the stop condition has been sent by the master, the internal programming cycle begins. at this point, all received data is written to the cat1024/25 in a single write cycle. figure 8. byte write timing figure 9: page write timing byte address slave address s a c k a c k data a c k s t o p p bus activity: master sda line s t a r t bus activity: master sda line data n+15 byte address (n) a c k a c k data n a c k s t o p s a c k data n+1 a c k s t a r t p slave address
cat1024, cat1025 doc. no. md-3008 rev. q 12 ? 2009 scillc. all rights reserved. characteristics subject to change without notice acknowledge polling disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host?s write opration, the cat1024/25 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave addre ss for a write operation. if the device is still busy with the write operation, no ack will be returned. if a write operation has completed, an ack will be returned and the host can then proceed with the next read or write operation. write protection pin (wp) the write protection feature (cat1025 only) allows the user to protect against inadvertent memory array programming. if the wp pin is tied to v cc , the entire memory array is protected and becomes read only. the cat1025 will ac cept both slave and byte addre- sses, but the memory location accessed is protected from programming by the device?s failure to send an acknowledge after the first by te of data is received. read operations the read operation for the cat1024/25 is initiated in the same manner as the write operation with one exception, the r/w bit is set to one. three different read operations are possible: immediate/current address read, selective/random read and sequential read. figure 10. immediate address read timing scl sda 8th bi t stop no ack data out 89 slave address s a c k data n o a c k s t o p p bus activit y: master sda line s t a r t
cat1024, cat1025 ? 2009 scillc. all rights reserved. 13 doc. no. md-3008 rev. q characteristics subject to change without notice immediate/current address read the cat1024 and cat1025 address counter contains the address of the last byte accessed, incremented by one. in other words, if the last read or write access was to address n, the read immediately following would access data from address n + 1. for n = e = 255, the counter will wrap around to zero and continue to clock out valid data. after the cat1024/1025 receives its slave address information (with the r/w bit set to one), it issues an acknowledge, then transmits the 8-bit byte requested. the master device does not send an acknowledge, but will generate a stop condition. selective/random read selective/random read operations allow the master device to select at random any memory location for a read operation. the master device first performs a ?dummy? write operation by sending the start condition, slave address and byte addresses of the location it wishes to read. after the cat1024 and cat1025 acknowledges, the master device sends the start condition and the slave address again, this time with the r/w bit set to one. the cat1024 and cat1025 then responds with its acknowledge and sends the 8-bit byte requested. the master device does not send an acknowledge but will generate a stop condition. sequential read the sequential read operation can be initiated by either the immediate address read or selective read operations. after the cat1024 and cat1025 sends the inital 8-bit byte requested, the master will responds with an acknowledge which tells the device it requires more data. the cat1024 and cat1025 will continue to output an 8-bit byte for each acknowledge, thus sending the stop condition. the data being transmitted from the cat1024 and cat1025 is sent sequentia lly with the data from address n followed by data from address n + 1. the read operation address counter increments all of the cat1024 and cat1025 address bits so that the entire memory array can be read during one operation. figure 11. selective read timing figure 12. sequential read timing slave address s a c k n o a c k s t o p p bus activity: master sda line s t a r t byte address (n) s a c k data n slave address a c k s t a r t bus activity: master sda line data n+x data n a c k a c k data n+1 a c k s t o p n o a c k data n+2 a c k p slave address
cat1024, cat1025 doc. no. md-3008 rev. q 14 ? 2009 scillc. all rights reserved. characteristics subject to change without notice package outline drawings pdip 8-lead 300mils (l) (1)(2) notes: (1) all dimensions are in millimeters. (2) complies with jedec ms-001. e1 d a l eb b2 a1 a2 e eb c top view side view end view pin # 1 identification symbol min nom max a5.33 a1 0.38 a2 2.92 3.30 4.95 b 0.36 0.46 0.56 b2 1.14 1.52 1.78 c 0.20 0.25 0.36 d 9.02 9.27 10.16 e 7.62 7.87 8.25 e 2.54 bsc e1 6.10 6.35 7.11 eb 7.87 10.92 l 2.92 3.30 3.80 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat1024, cat1025 ? 2009 scillc. all rights reserved. 15 doc. no. md-3008 rev. q characteristics subject to change without notice soic 8-lead 150mils (w) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec ms-012. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e1 e a a1 h l c e b d pin # 1 identification top view side view end view a1.35 1.75 a1 0.10 0.25 b0.33 0.51 c0.19 0.25 d4.80 5.00 e5.80 6.20 e1 3.80 4.00 e 1.27 bsc h0.25 0.50 l0.40 1.27 0o 8o symbol min nom max
cat1024, cat1025 doc. no. md-3008 rev. q 16 ? 2009 scillc. all rights reserved. characteristics subject to change without notice tssop 8-lead (v) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-153 a2 e1 e a1 e b d c a top view side view end view 1 l1 l symbol min nom max a1.20 a1 0.05 0.15 a2 0.80 0.90 1.05 b 0.19 0.30 c 0.09 0.20 d 2.90 3.00 3.10 e 6.30 6.40 6.50 e1 4.30 4.40 4.50 e0.65 bsc l1.00 ref l1 0.50 0.60 0.75 10 8 for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat1024, cat1025 ? 2009 scillc. all rights reserved. 17 doc. no. md-3008 rev. q characteristics subject to change without notice msop 8-lead (z) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-187. e1 e a2 a1 e b d c a top view side view end view l1 l2 l detail a detail a symbol min nom max a1.10 a1 0.05 0.10 0.15 a2 0.75 0.85 0.95 b 0.22 0.38 c 0.13 0.23 d 2.90 3.00 3.10 e 4.80 4.90 5.00 e1 2.90 3.00 3.10 e 0.65 bsc l 0.40 0.60 0.80 l1 0.95 ref l2 0.25 bsc 0o 6o for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf.
cat1024, cat1025 doc. no. md-3008 rev. q 18 ? 2009 scillc. all rights reserved. characteristics subject to change without notice tdfn 8-pad 3 x 3mm (zd4) (1)(2) notes: (1) all dimensions are in millimeters. angles in degrees. (2) complies with jedec mo-229. for current tape and reel information, download the pdf file from: http://www.catsemi.com/documents/tapeandreel.pdf. e2 a3 eb a a1 side view bottom view e d top view pin#1 index area pin#1 id front view a1 a l d2 symbol min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a3 0.20 ref b 0.23 0.30 0.37 d 2.90 3.00 3.10 d2 2.20 2.30 2.40 e 2.90 3.00 3.10 e2 1.40 1.50 1.60 e0.65typ l 0.20 0.30 0.40
cat1024, cat1025 ? 2009 scillc. all rights reserved. 19 doc. no. md-3008 rev. q characteristics subject to change without notice example of ordering information (1) ordering part number ? cat1024xx ordering part number ? cat1025xx cat1024li-45-g cat1024zi-45-gt3 cat1025li-45-g cat1025zi-45-gt3 cat1024li-42-g cat1024zi-42-gt3 cat1025li-42-g cat1025zi-42-gt3 cat1024li-30-g cat1024zi-30-gt3 cat1025li-30-g cat1025zi-30-gt3 cat1024li-28-g cat1024zi-28-gt3 cat1025li-28-g cat1025zi-28-gt3 cat1024li-25-g cat1024zi-25-gt3 cat1025li-25-g cat1025zi-25-gt3 cat1024wi-45-gt3 cat1024zd4i-45-t3 cat1025wi-45-gt3 cat1025zd4i-45-t3 cat1024wi-42-gt3 cat1024zd4i-42-t3 cat1025wi-42-gt3 cat1025zd4i-42-t3 cat1024wi-30-gt3 CAT1024ZD4I-30-T3 cat1025wi-30-gt3 cat1025zd4i-30-t3 cat1024wi-28-gt3 cat1024zd4i-28-t3 cat1025wi-28-gt3 cat1025zd4i-28-t3 cat1024wi-25-gt3 cat1024zd4i-25-t3 cat1025wi-25-gt3 cat1025zd4i-25-t3 cat1024yi-45-gt3 cat1025yi-45-gt3 cat1024yi-42-gt3 cat1025yi-42-gt3 cat1024yi-30-gt3 cat1025yi-30-gt3 cat1024yi-28-gt3 cat1025yi-28-gt3 cat1024yi-25-gt3 cat1025yi-25-gt3 notes: (1) all packages are rohs-compliant (lead-free, halogen-free). (2) the standard lead finish is nipdau. (3) the device used in the above example is a cat1024wi-30-gt3 (soic, industrial temperature, 3.0 - 3.15v, nipdau, tape & reel) . (4) for additional package and temperatur e options, please contact your neares t on semiconductor sales office. (5) tdfn not available in nipdau (?g) version. prefix device # suffix cat 1024 w i -30 ? g t3 company id package l: pdip w: soic y: tssop z: msop zd4: tdfn 3 x 3mm (5) temperature range i = in dust ri a l ( - 4 0 o c to 85 o c) reset threshold voltage -45: 4.50v ? 4.75v -42: 4.25v ? 4.50v -30: 3.00v ? 3.15v -28: 2.85v ? 3.00v -25: 2.55v ? 2.70v product number 1024: 2k 1025: 2k tape & reel t: tape & reel 3: 3000/reel lead finish blank: matte-tin g: nipdau
cat1024, cat1025 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes with out further notice to any products herein. scillc make s no warranty, representa tion or guarantee regarding the suit ability of its products for any pa rticular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer's technical experts. sci llc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly o r indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufact ure of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information literature fulfillment: literature distribution ce nter for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone: 303-675-2175 or 800-344-3860 toll free usa/canada fax: 303-675-2176 or 800-344-3867 toll free usa/canada email: orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center: phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature: http://www.onsemi.com/orderlit for additional information, please contact your local sales representative doc. no. md-3008, rev. q 20 ? 2009 scillc. all rights reserved. characteristics subject to change without notice revision history date rev. description 7-nov-03 i eliminated automotive temperature range 12-apr-04 j eliminated data sheet designation updated reel ordering information 1-nov-04 k changed soic package designators eliminated 8-pad tdfn (3 x 4.9mm) package added package outlines 4-nov-04 l update pin configuration 11-nov-04 m update feature update description update dc operating characteristic update ac characteristics 2-feb-07 n update example of ordering information 28-nov-07 o update package outline drawings update example of ordering information add ?md-? to document number 07-nov-08 p change logo and fine print to on semiconductor 05-mar-09 q update ordering information (remove 2,000/reel)

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